1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming non-continuous conductive layers for conductive structures formed on an integrated circuit product and the resulting structures.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires a large number of circuit elements, such as transistors, capacitors, resistors, etc., to be formed on a given chip area according to a specified circuit layout. During the fabrication of complex integrated circuits using, for instance, MOS (Metal-Oxide-Semiconductor) technology, millions of transistors, e.g., N-channel transistors (NFETs) and/or P-channel transistors (PFETs), are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an NFET transistor or a PFET transistor is considered, typically includes doped source and drain regions that are formed in a semiconducting substrate and separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region.
To improve the operating speed of field effect transistors (FETs), and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the past decades. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs and the overall functionality of the circuit. Further scaling (reduction in size) of the channel length of transistors is anticipated in the future. While this ongoing and continuing decrease in the channel length of transistor devices has improved the operating speed of the transistors and integrated circuits that are formed using such transistors, there are certain problems that arise with the ongoing shrinkage of feature sizes that may at least partially offset the advantages obtained by such feature size reduction. For example, as the channel length is decreased, the pitch between adjacent transistors likewise decreases, thereby increasing the density of transistors per unit area. This scaling also limits the size of the conductive contact elements and structures, which has the effect of increasing their electrical resistance. In general, the reduction in feature size and increased packing density makes everything more crowded on modern integrated circuit devices.
Typically, due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements cannot be established within the same level on which the circuit elements, such as transistors, are manufactured. Rather, modern integrated circuit products have multiple so-called metallization layer levels that, collectively, contain the “wiring” pattern for the product, i.e., the conductive structures that provide electrical connection to the transistors and the circuits, such as conductive vias and conductive metal lines. In general, the conductive metal lines are used to provide intra-level (same level) electrical connections, while interlevel (between levels) connections or vertical connections are referred to as vias. In short, the vertically oriented conductive via structures provide the electrical connection between the various stacked metallization layers. Accordingly, the electrical resistance of such conductive structures, e.g., lines and vias, becomes a significant issue in the overall design of an integrated circuit product, since the cross-sectional area of these elements is correspondingly decreased, which may have a significant influence on the effective electrical resistance and overall performance of the final product or circuit.
Improving the functionality and performance capability of various metallization systems has also become an important aspect of designing modern semiconductor devices. One example of such improvements is reflected in the increased use of copper metallization systems in integrated circuit devices and the use of so-called “low-k” dielectric materials (materials having a dielectric constant less than about 3) in such devices. Copper metallization systems exhibit improved electrical conductivity as compared to, for example, prior metallization systems that used tungsten for the conductive lines and vias. The use of low-k dielectric materials tends to improve the signal-to-noise ratio (S/N ratio) by reducing cross-talk as compared to other dielectric materials with higher dielectric constants. However, the use of such low-k dielectric materials can be problematic as they tend to be less resistant to metal migration as compared to some other dielectric materials.
Copper is a material that is difficult to directly etch using traditional masking and etching techniques. Thus, conductive copper structures, e.g., conductive lines or vias, in modern integrated circuit devices are typically formed using known single or dual damascene techniques. FIGS. 1A-1B depict one illustrative prior art technique for forming a conductive copper structure. In general, the damascene technique involves: (1) forming one or more trenches/vias 12 in a layer of insulating material 14; (2) depositing one or more relatively thin barrier layers 16 (e.g., TiN, TaN); (3) forming an adhesion or wetting layer 18 (e.g., tantalum, ruthenium, etc.) on the barrier layer 16; (4) forming a copper seed layer (not shown) comprised of, for example, pure copper, copper-manganese, copper-aluminum, etc.; (5) forming a bulk copper material 20 across the substrate and in the trenches/vias 12; and (6) performing a chemical mechanical polishing process to remove the excess portions of the barrier layer 16, the adhesion layer 18 and the copper material 20 positioned outside of the trenches/vias 12 to define the illustrative final conductive copper structures 22 depicted in FIG. 1B. As is well known to those skilled in the art, the copper material 20 is typically formed by performing an electrochemical copper deposition process after a thin conductive copper seed layer (not shown in FIG. 1A) is deposited by physical vapor deposition on the adhesion layer 18.
However, as everything becomes more crowded on an integrated circuit product, problems may arise when manufacturing conductive structures employing traditional damascene techniques. More specifically, in conventional processing, the barrier layer 16, the liner layer 18 and the copper seed layer (not shown) all are formed as continuous individual layers, and the barrier layer 16 and the liner layer 18 are typically made of materials that are less conductive than copper. As the overall size of the conductive structure is reduced, the barrier layer 16 and the liner layer 18 occupy an increasing proportion of the space allowed for the overall conductive structure. Accordingly, the electrical resistance of the overall conductive structure increases. Additionally, the uniform barrier layers and liner layers used in high performance integrated circuit products are being manufactured to very small thicknesses that are about at the limits of the production equipment, i.e., it is difficult to continue to reduce the thickness of the barrier layers and the liner layers. Another problem encountered in manufacturing conductive structures using existing techniques is that the various anneals that are performed on the barrier layer 16 may result in the formation of so-called “open-pipe” copper diffusion paths in the barrier layer, and such anneals may weaken the interface between the barrier layer 16 and the layer of insulating material 14. Simply put, that anneal of the barrier layer 16 may cause uncontrolled recovery and re-crystallization of the microstructure of the material of the barrier layer 16. In some situations, semiconductor manufacturers have started to use materials such as ruthenium as the liner layer 18 to facilitate copper filling of the trench/via 12. While ruthenium improves copper filling characteristics, its use as an adhesion layer material is not without problems. Ruthenium typically causes a pseudo-corrosive reaction with tantalum, a common material in barrier layers. In turn, such a reaction may cause an undesirable increase in the resistance of the conductive structure, create open pathways in the barrier layer and generally degrade the overall quality of the barrier layer.
The present disclosure is directed to various methods of forming non-continuous conductive layers for conductive structures formed on an integrated circuit product, such as conductive lines/vias, that may solve or at least reduce some of the problems identified above.